The present invention relates to a register addressing technique particularly but not exclusively designed to facilitate register accesses in a processor. The invention also relates to a computer system in which register addresses are generated.
In computer systems it is conventional to define in each instruction to be executed a set of register addresses which are used to access a register file in the computer system. The register addresses normally include first and second source register addresses defining registers from which operands are extracted and at least one destination register address defining a register into which the results of an operation are loaded. Data processing instructions generally use the contents of the first and second source registers in some defined mathematical or logical manipulation and load the results of that manipulation into the defined destination register. Memory access instructions use the register addresses to define memory locations for loading and storing data to and from a data memory. In a load instruction, the source registers define a memory location from which data is to be loaded into the destination register. In a store instruction, the source registers define a memory location into which data is to be stored from the destination register.
Some computer systems have more than one execution channel. In such computer systems, each execution channel has a number of functional units which can operate independently. Both execution channels can be in use simultaneously. Sometimes, the execution channels share a common register file. It is useful in such architectures to provide instructions which simultaneously instruct both execution channels to implement a function so as to speed up operation of the processor. In such a scenario, a so-called long instruction may have two instruction portions each intended for a particular execution channel. Each instruction portion needs to define the register addresses for use in the function to be performed by the execution channel for which it is intended. In some cases both instruction portions may wish to define associated or the same register addresses. In these situations a long instruction needs to define two sets of register addresses, one for each execution channel.
It is an aim of the present invention to reduce the number of bits required in an instruction for accessing a register file, in particular in the context of multiple execution channels in a computer system.
According to one aspect of the present invention there is provided a computer system comprising: a decode unit for decoding instructions supplied to the decode unit from a program memory, wherein each instruction has at least one bit sequence defining a register address; a register file having a plurality of registers each having the same predetermined bit capacity and addressable via at least two register address ports, one of said ports being associated with a first execution channel of the computer system and the other of said ports being associated with the second execution channel of the computer system; a first register address supply path for supplying said at least one bit sequence in the instruction to said one register address port; and a second register address path for supplying the bit sequence in the instruction to said other register address port via a unitary operator which selectively alters the logical value of at least one bit in the register address dependent on the logical value of said at least one bit.
According to another aspect of the invention there is provided a method of accessing a register file, the method comprising: defining a first register address as a plurality of bits and using said first register address to access said register file; generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file.
That is, in one embodiment, if the LSB (least significant bit) of the sequence is a xe2x80x9czerosxe2x80x9d, it is changed to a xe2x80x9conexe2x80x9d by the unitary operator, but if it is a one, it remains unchanged. Thus, the bit sequence ending in a xe2x80x9czeroxe2x80x9d generates an even/odd pair of register addresses and the bit sequence ending in a xe2x80x9conexe2x80x9d generates an odd/odd pair.